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PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
Rev. 03 -- 18 April 2005 Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOSTM technology.
1.2 Features
s Logic level threshold s Lead-free construction s Very low on-state resistance s Low gate charge
1.3 Applications
s DC-to-DC converter s Switch-mode power supplies
1.4 Quick reference data
s VDS 25 V s RDSon 6 m s ID 75 A s Qgd = 5.6 nC (typ)
2. Pinning information
Table 1: Pin 1 2 3 mb Pinning Description gate (G) drain (D) source (S) mounting base; connected to drain
2 1 3 1 2 3 1 2 3
[1]
Simplified outline
mb mb mb
Symbol
D
G
mbb076
S
SOT404 (D2PAK)
[1]
SOT428 (DPAK)
SOT533 (IPAK)
It is not possible to make a connection to pin 2 of the SOT404 and SOT428 packages.
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
3. Ordering information
Table 2: Ordering information Package Name PHB108NQ03LT PHD108NQ03LT PHU108NQ03LT D2PAK DPAK IPAK Description Version plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT404 plastic single-ended surface mounted package; 3 leads (one lead cropped) SOT428 plastic single-ended package; 3 leads (in-line) SOT533 Type number
4. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tmb = 25 C peak source (diode forward) current Tmb = 25 C; pulsed; tp 10 s unclamped inductive load; ID = 43 A; tp = 0.25 ms; VDD 25 V; RGS = 50 ; VGS = 10 V; starting at Tj = 25 C Tmb = 25 C; VGS = 5 V; Figure 2 and 3 Tmb = 100 C; VGS = 5 V; Figure 2 Tmb = 25 C; pulsed; tp 10 s; Figure 3 Tmb = 25 C; Figure 1 Conditions 25 C Tj 175 C 25 C Tj 175 C; RGS = 20 k Min -55 -55 Max 25 25 20 75 75 240 187 +175 +175 75 240 180 Unit V V V A A A W C C A A mJ
Source-drain diode
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy
9397 750 14707
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
2 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
120 Pder (%) 80
03aa16
120 Ider (%) 80
03ar58
40
40
0 0 50 100 150 Tmb (C) 200
0 0 50 100 150 Tmb (C) 200
P tot P der = ------------------------ x 100 % P
tot ( 25 C )
ID I der = -------------------- x 100 % I
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of mounting base temperature
103 ID (A) 102 Limit RDSon = VDS / ID
Fig 2. Normalized continuous drain current as a function of mounting base temperature
03ar59
tp = 10 s 100 s
DC 10
1 ms 10 ms
1 1 10 VDS (V) 102
Tmb = 25 C; IDM is single pulse; VGS = 5 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9397 750 14707
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
3 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
5. Thermal characteristics
Table 4: Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Min Typ 50 Max 0.8 Unit K/W K/W thermal resistance from junction to mounting base Figure 4 thermal resistance from junction to ambient SOT404 mounted on a printed-circuit board; minimum footprint; vertical in still air mounted on a printed-circuit board; minimum footprint; vertical in still air mounted on a printed-circuit board; vertical in still air; SOT404 minimum footprint SOT533 vertical in free air Symbol Parameter
SOT428
-
75
-
K/W
-
50
-
K/W
-
70
-
K/W
1 = 0.5
03ar60
Zth(j-mb) (K/W)
0.2 10-1 0.1 0.05
P tp T
=
0.02 single pulse
tp
t T
10-2 10-5
10-4
10-3
10-2
10-1
tp (s)
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
9397 750 14707
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
4 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
6. Characteristics
Table 5: Characteristics Tj = 25 C unless otherwise specified. Symbol V(BR)DSS Parameter drain-source breakdown voltage Conditions ID = 250 A; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Figure 9 and 10 Tj = 25 C Tj = 175 C Tj = -55 C IDSS drain-source leakage current VDS = 25 V; VGS = 0 V Tj = 25 C Tj = 175 C RG IGSS RDSon gate resistance gate-source leakage current drain-source on-state resistance f = 1 MHz VGS = 10 V; VDS = 0 V VGS = 5 V; ID = 25 A; Figure 6 and 8 Tj = 25 C Tj = 175 C VGS = 10 V; ID = 25 A; Figure 6 and 8 Dynamic characteristics Qg(tot) Qgs Qgs1 Qgs2 Qgd Vplat Qg(tot) Ciss Coss Crss Ciss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge pre-VGS(th) gate-source charge post-VGS(th) gate-source charge gate-drain (Miller) charge plateau voltage total gate charge input capacitance output capacitance reverse transfer capacitance input capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 25 A; VGS = 0 V; Figure 13 reverse recovery time recovered charge IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V; VR = 25 V VGS = 0 V; VDS = 0 V; f = 1 MHz VDS = 12 V; RL = 0.5 ; VGS = 4.5 V; RG = 5.6 ID = 0 A; VDS = 0 V; VGS = 4.5 V VGS = 0 V; VDS = 12 V; f = 1 MHz; Figure 14 ID = 25 A; VDS = 12 V; VGS = 4.5 V; Figure 11 and 12 16.3 4 2.5 1.5 5.6 2.4 12.5 640 250 2120 15 38 32 25 0.86 34 21 1.2 nC nC nC nC nC V nC pF pF pF pF ns ns ns ns V ns nC 6.7 12.1 5.3 7.5 13.5 6 m m m 1.2 0.02 1 500 100 A A nA 1 0.5 1.5 2 2.2 V V V 25 22 V V Min Typ Max Unit Static characteristics
1375 -
Source-drain diode
9397 750 14707
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
5 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
80 ID (A) 60 VGS (V) =
03ar61
10 6 5 4.5
4 3.5
15 VGS (V) = RDSon (m) 10
03ar62
3.5
4 3 40 4.5 5 6 10
5 20 2.5
2 0 0 0.2 0.4 0.6 0.8 VDS (V) 1 0 0 20 40 60 ID (A) 80
Tj = 25 C
Tj = 25 C
Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values
80 ID (A) 60
03ar63
Fig 6. Drain-source on-state resistance as a function of drain current; typical values
2 a 1.5
03af18
40
1
20 Tj = 175 C 25 C
0.5
0 0 1 2 3 VGS (V) 4
0 -60
0
60
120
Tj (C)
180
Tj = 25 C and 175 C; VDS > ID x RDSon
R DSon a = ----------------------------R DSon ( 25 C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature
Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values
9397 750 14707
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
6 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
2.5 VGS(th) (V) 2 max
03aa33
10-1 ID (A) 10-2
03aa36
1.5
typ
10-3 min typ max
1
min
10-4
0.5
10-5
0 -60
10-6 0 60 120 Tj (C) 180 0 1 2 VGS (V) 3
ID = 1 mA; VDS = VGS
Tj = 25 C; VDS = 5 V
Fig 9. Gate-source threshold voltage as a function of junction temperature
10 VGS (V) 8
03ar64
Fig 10. Sub-threshold drain current as a function of gate-source voltage
ID = 25 A Tj = 25 C
VDS ID
6 12 V 4
VGS(th)
VDS = 19 V
Vplat
2
VGS Qgs1 Qgs2 Qgs Qgd Qg(tot)
003aaa508
0 0 10 20 30 QG (nC) 40
ID = 25 A; VDS = 12 V and 19 V
Fig 11. Gate-source voltage as a function of gate charge; typical values
Fig 12. Gate charge waveform definitions
9397 750 14707
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
7 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
80 IS (A) 60
03ar65
104 C (pF)
03ar66
Ciss 40 103 Coss
175 C 20
Tj = 25 C
Crss 0 0.2 102 10-1
0.4
0.6
0.8
1
VSD (V)
1.2
1
10
VDS (V)
102
Tj = 25 C and 175 C; VGS = 0 V
VGS = 0 V; f = 1 MHz
Fig 13. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
4000 C (pF) 3000
Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
03ar67
Ciss
2000
Crss
1000
0 0 2 4 6 8 VGS (V) 10
VDS = 0 V
Fig 15. Input and reverse transfer capacitances as a function of gate-source voltage; typical values
9397 750 14707
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
8 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
7. Package outline
Plastic single-ended surface mounted package (D2PAK); 3 leads (one lead cropped)
SOT404
A E A1 mounting base
D1
D
HD
2
Lp
1
3
b c Q
e
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.80 14.80 Q 2.60 2.20
OUTLINE VERSION SOT404
REFERENCES IEC JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 04-10-13 05-02-11
Fig 16. Package outline SOT404 (D2PAK)
9397 750 14707 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
9 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
Plastic single-ended surface mounted package (DPAK); 3 leads (one lead cropped)
SOT428
y E b2 A A1 A E1
mounting base D1 HD
D2
2 L2 1 3
L L1
b1 e e1
b
w
M
A
c
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1 0.93 0.73 b 0.89 0.71 b1 1.1 0.9 b2 5.46 5.00 c 0.56 0.20 D1 6.22 5.98 D2 min 4.0 E 6.73 6.47 E1 min 4.45 e 2.285 e1 4.57 HD 10.4 9.6 L 2.95 2.55 L1 min 0.5 L2 0.9 0.5 w 0.2 y max 0.2
OUTLINE VERSION SOT428
REFERENCES IEC JEDEC TO-252 JEITA SC-63
EUROPEAN PROJECTION
ISSUE DATE 05-02-09 05-02-11
Fig 17. Package outline SOT428 (DPAK)
9397 750 14707 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
10 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
Plastic single-ended package (IPAK); 3 leads (in-line)
SOT533
E E1 A1
A
D1 mounting base D2
L1 Q
L
1
2
3
e1 e
b
w
M
c
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1 0.89 0.71 b 0.89 0.71 c 0.56 0.46 D1 1.10 0.96 D2 6.23 5.97 E 6.73 6.47 E1 e e1 L 9.6 9.2 L1 (2) max 2.7 Q 1.1 1.0 w 0.3
2.285 5.21 4.57 5.00 BSC (1) BSC (1)
Notes 1. Basic spacing between centers. 2. Terminal dimensions are uncontrolled within zone L1. OUTLINE VERSION SOT533 REFERENCES IEC JEDEC TO-251 JEITA EUROPEAN PROJECTION ISSUE DATE 04-09-22 05-02-11
Fig 18. Package outline SOT533 (IPAK)
9397 750 14707
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
11 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
8. Revision history
Table 6: Revision history Release date 20050418 Data sheet status Change notice Doc. number 9397 750 14707 Supersedes PHP_PHB_PHD108NQ03LT-02 Document ID PHB_PHD_PHU108NQ03LT_3 Modifications:
Product data 2004070095 sheet
* * * * * * * * *
The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. Removal of PHP108NQ03LT Addition of PHU108NQ03LT Section 4 "Limiting values" ID, IDM, Ptot and ISM data corrected. Table 5 "Characteristics" RDSon, Qg(tot), Qgs, Qgd, Ciss, Coss, Crss, td(on), tr, td(off), tf and Qr test conditions and/or typical values modified. Table 5 "Characteristics" RG, Qgs1, Qgs2 and Vplat tests added. Table 5 "Characteristics" VGS(th), Ciss, Crss and Qg(tot) data added. Figure 2, 3, 4, 5, 6, 7, 8, 11,13 and 14 modified. Figure 12 and 15 added. Product data Product data 9397 750 10159 9397 750 09065 PHP_PHB_PHD108NQ03LT-01 -
PHP_PHB_PHD108NQ03LT-02 PHP_PHB_PHD108NQ03LT-01
20020911 20011218
9397 750 14707
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
12 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
9. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
10. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
12. Trademarks
TrenchMOS -- is a trademark of Koninklijke Philips Electronics N.V.
11. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
13. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14707
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 18 April 2005
13 of 14
Philips Semiconductors
PHB/PHD/PHU108NQ03LT
N-channel TrenchMOSTM logic level FET
14. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 12 13 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information . . . . . . . . . . . . . . . . . . . . 13
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 18 April 2005 Document number: 9397 750 14707
Published in The Netherlands

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